Configurable Microprocessor Array for DSP Applications
نویسندگان
چکیده
The approach for mapping parallel algorithms into FPGA is proposed, which is based on programming the con ̄gurable microprocessor array. Each cell of this array is the microprocessor with RISC architecture represented as a soft IP-core. The hardware volume of the microprocessor soft core is minimized, and adapted to the used instruction subset. The approach provides both high throughput and minimized hardware volume, and speedups the design process. The approach was proven in the microprocessor array for solving the linear equation system with the Toeplitz matrix.
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